IRIS
DE CARO, Davide
 Distribuzione geografica
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Continente #
EU - Europa 2.677
NA - Nord America 2.409
AS - Asia 1.269
SA - Sud America 149
AF - Africa 6
Continente sconosciuto - Info sul continente non disponibili 4
OC - Oceania 1
Totale 6.515
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Nazione #
US - Stati Uniti d'America 2.377
RU - Federazione Russa 1.081
IT - Italia 866
SG - Singapore 623
CN - Cina 284
HK - Hong Kong 234
UA - Ucraina 166
DE - Germania 138
BR - Brasile 137
FI - Finlandia 122
IE - Irlanda 92
GB - Regno Unito 52
KR - Corea 41
SE - Svezia 39
FR - Francia 36
IN - India 31
CA - Canada 28
AT - Austria 23
TR - Turchia 23
NL - Olanda 21
PL - Polonia 12
AR - Argentina 6
TW - Taiwan 6
BD - Bangladesh 5
CH - Svizzera 5
CZ - Repubblica Ceca 5
EU - Europa 4
IR - Iran 4
RO - Romania 4
CI - Costa d'Avorio 3
DK - Danimarca 3
ES - Italia 3
BE - Belgio 2
BG - Bulgaria 2
JP - Giappone 2
LT - Lituania 2
MX - Messico 2
PK - Pakistan 2
PY - Paraguay 2
VE - Venezuela 2
AE - Emirati Arabi Uniti 1
AU - Australia 1
BS - Bahamas 1
CO - Colombia 1
HU - Ungheria 1
ID - Indonesia 1
IL - Israele 1
IQ - Iraq 1
KE - Kenya 1
KG - Kirghizistan 1
KW - Kuwait 1
LU - Lussemburgo 1
MO - Macao, regione amministrativa speciale della Cina 1
MY - Malesia 1
NG - Nigeria 1
OM - Oman 1
PA - Panama 1
PH - Filippine 1
PS - Palestinian Territory 1
RS - Serbia 1
SA - Arabia Saudita 1
UY - Uruguay 1
UZ - Uzbekistan 1
VN - Vietnam 1
ZA - Sudafrica 1
Totale 6.515
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Città #
Singapore 421
Chandler 402
Moscow 276
Santa Clara 272
Hong Kong 230
Naples 209
Jacksonville 171
Napoli 117
Millbury 102
Ashburn 94
Princeton 90
Nanjing 70
Hefei 67
Boston 66
Fairfield 63
Wilmington 61
Boardman 46
Beijing 45
Milan 41
Seoul 40
Helsinki 36
Des Moines 35
Kronberg 34
Woodbridge 24
Ottawa 19
Nuremberg 18
Nanchang 17
Seattle 17
The Dalles 17
Amsterdam 15
Ann Arbor 15
Castellammare Di Stabia 15
Hebei 14
Lawrence 14
Frankfurt am Main 13
Rome 13
Shenyang 13
São Paulo 13
Falkenstein 12
New York 12
Norwalk 12
Jiaxing 11
Los Angeles 11
Duncan 10
Florence 10
Hyderabad 10
Istanbul 10
Brooklyn 8
Changsha 8
Guangzhou 8
Indiana 8
Pescara 8
Redwood City 8
Salerno 8
San Francisco 8
Bexley 7
Tianjin 7
Orta 6
Rio de Janeiro 6
Roubaix 6
Sarno 6
Shanghai 6
Springfield 6
Vienna 6
Warsaw 6
Carinola 5
Lauria 5
London 5
Montoro 5
Munich 5
Nocera Superiore 5
Orange 5
Washington 5
Ankara 4
Campinas 4
Dublin 4
Houston 4
Kunming 4
Liscate 4
Ottaviano 4
Palermo 4
Sant'Antonio Abate 4
Taranto 4
Trieste 4
Udine 4
Belo Horizonte 3
Caserta 3
Catania 3
Chicago 3
Geneva 3
Giugliano In Campania 3
Horia 3
Limbiate 3
Lusciano 3
Petrópolis 3
Pompei 3
Portici 3
Pune 3
Rende 3
San Ginesio 3
Totale 3.582
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Nome #
A Context-Aware Multimedia Recommender System for activities planning in mobile environments 115
A 3.3 GHz Spread-Spectrum Clock Generator Supporting Discontinuous Frequency Modulations in 28 nm CMOS 110
Approximate Multipliers Using Static Segmentation: Error Analysis and Improvements 108
Single Bit Filtering Circuit Implemented in a System for the Generation of Colored Noise 106
A high-speed sense-amplifier based flip-flop 102
A 1.27GHz, All-Digital Spread Spectrum Clock Generator-Synthesizer in 65nm CMOS 101
Salviamo l’università, la ricerca e, perchè no, professori e ricercatori 99
On the Use of Approximate Multipliers in LMS Adaptive Filters 97
A 41 ps ASIC time-to-digital converter for physics experiments 91
A 1.45 GHz All-Digital Spread Spectrum Clock Generator in 65nm CMOS for Synchronization Free SoC Applications 91
Mux-based Digital Delay Interpolator 84
Minimizing Coefficients Wordlength for Piecewise-Polynomial Hardware Function Evaluation With Exact or Faithful Rounding 84
Single Flip-flop Driving Circuit for glitch-free NAND-based Digitally Controlled Delay-Lines 79
Approximate Multipliers Based on New Approximate Compressors 77
A novel high-speed sense-amplifier-based flip-flop 76
A SISO register circuit tailored for input data with low transition probability 75
Stall-Aware Fixed-Point Implementation of LMS Filters 74
Design of low-power approximate LMS filters with precision-scalability 74
An area-efficient high-speed Reed-Solomon decoder in 0.25um CMOS 73
Dual-tree error compensation for high performance fixed-width multipliers 70
Variable Latency Speculative Han-Carlson Adder 70
Approximate adder with output correction for error tolerant applications and Gaussian distributed inputs 70
Approximate Floating-Point Multiplier based on Static Segmentation 69
An experimental power-lines model for digital ASICs based on transmission-lines 69
Direct Digital Frequency Synthesizer Using Non-Uniform Piecewise-Linear Approximation 69
Novel Low-Power Floating-Point Divider With Linear Approximation and Minimum Mean Relative Error 68
An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy 68
High-speed Direct Digital Frequency Synthesizers in 0.25-um CMOS 67
Variable latency speculative Han-Carlson adders topologies 67
Truncated Squarer with Minimum Mean-Square Error 66
Design of Generalized Enhanced Static Segment Multiplier with Minimum Mean Square Error for Uniform and Nonuniform Input Distributions 65
A Novel Truncated Squarer with Linear Compensation Function 65
On the Use of Approximate Adders in Carry-Save Multiplier-Accumulators 65
A Novel Module-Sign Low-Power Implementation for the DLMS Adaptive Filter with Low Steady-State Error 65
A High Speed Differential Resistor Ladder 64
A Standard-Cell-Based All-Digital PWM Modulator With High Resolution and Spread-Spectrum Capability 64
ROM-less Direct Digital Frequency Synthesizers exploiting Polynomial Approximation 63
A high performance floating-point special function unit using constrained piecewise quadratic approximation 63
Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers 63
Accurate Fixed-Point Logarithmic Converter 62
A 630MHz Direct Digital Frequency Synthesizer with 90dBc SFDR in 0.25um CMOS 61
Low-Power Hardware Implementation of Least-Mean-Square Adaptive Filters Using Approximate Arithmetic 61
Design criteria of high voltage Superjunction Merged PiN Schottky diode 60
Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed Operands 60
An Efficient Digital Background Control for Hybrid Transformer-Based Receivers 60
FPGA architecture for real time video segmentation and denoising 59
Analysis and comparison of Direct Digital Frequency Synthesizers implemented on FPGA 59
Real-Time Implementation of a Frequency Shifter for Enhancement of Heart Sounds Perception on VLIW DSP Platform 59
High Speed Differential Resistor Ladder for A/D Converters 58
A novel low-power DLMS adaptive filter with sign-magnitude learning and approximated FIR section 57
Direct Digital Frequency Synthesizers using high-order Polynomial Approximation 57
A 380MHz Direct Digital Synthesizer/Mixer with Hybrid CORDIC Architecture in 0.25um CMOS 57
A 430 MHz, 280 mW processor for the conversion of Cartesian to polar coordinates in 0.25um CMOS 57
Digital Synthesizer/Mixer with Hybrid CORDIC Multiplier Architecture: Error Analysis and Optimization 57
Design of Fixed-Width Multipliers with Linear Compensation Function 57
Approximate MAC unit using Static Segmentation 56
A Reconfigurable 2D Convolver for Real-Time SAR Imaging 56
A 2.5GHz DDFS-PLL with 1.8MHz bandwidth in 0.35um CMOS 56
An FDD Wireless Diversity Receiver With Transmitter Leakage Cancellation in Transmit and Receive Bands 56
A Binary Line Buffer Circuit Featuring Lossy Data Compression at Fixed Maximum Data Rate 56
A Novel Low-Power High-Precision Implementation for Sign–Magnitude DLMS Adaptive Filters 56
Fixed-Width CSD Multipliers with Minimum Mean Square Error 55
An FFT-based coprocessor for real time video processing 55
Real-time algorithm for Poissonian noise reduction in low-dose fluoroscopy: performance evaluation 55
Quality-Scalable Approximate LMS Filter 55
High Rate Data Down Link 54
VLSI Design of a (255,239) Reed-Solomon Decoder 54
Fixed-Width Multipliers and Multipliers-Accumulators With Min-Max Approximation Error 54
Design of fixed-width multipliers with minimum mean square error 53
A 380MHz, 150mW Direct Digital Synthesizer/Mixer in 0.25um CMOS 53
Low error Truncated Multipliers for DSP applications 53
FPGA Implementation of Gaussian Mixture Model Algorithm for 47fps Segmentation of 1080p Video 53
Variable-Rounded LMS Filter for Low-Power Applications 53
Direct digital frequency synthesizers with polynomial hyperfolding technique 52
A 630MHz, 76mW, Direct Digital Frequency Synthesizer Using Enhanced ROM Compression Technique 51
A Novel Architecture for Galois Fields GF(2^m) Multipliers Based on Mastrovito Scheme 51
Booth folding encoding for high performance squarer circuits 50
Tecniche polinomiali ROM-less per la realizzazione di circuiti per la sintesi digitale diretta ad elevate prestazioni 50
High Speed Speculative Multipliers Based on Speculative Carry-Save Tree 50
New clock gating techniques for low power flip-flops 49
Hardware implementation of a spatio-temporal average filter for real-time denoising of fluoroscopic images 49
Low-power Implementation of LMS Adaptive Filters Using Scalable Rounding 49
A Low Power Control System for Real-Time Tuning of a Hybrid Transformer-based Receiver 48
Low-power flip-flops with reliable clock-gating 47
New Design of Squarer Circuits Using Booth Encoding and Folding Techniques 47
High Performance Direct Digital Frequency Synthesizers Using Piecewise Polynomial Approximation 47
Analysis of spread-spectrum clocking modulations under synchronization timing constraint 47
Low-power approximate multiplier with error recovery using a new approximate 4-2 compressor 47
Low power flip-flop with clock gating on master and slave latches 46
Truncated Binary Multipliers with Variable Correction and Minimum Mean Square Error 46
B3X: a novel efficient algorithm for accurate automated auscultatory blood pressure estimation 45
Test Pattern Generator for Hybrid Testing of Combinational Circuits 45
Constrained Piecewise Polynomial Approximation for Hardware Implementation of Elementary Functions 45
Elementary Functions Hardware Implementation Using Constrained Piecewise Polynomial Approximations 45
Parallel squarer using Booth-folding technique 44
Shuffled Serial Adder: An Area-Latency Effective Serial Adder 44
Direct Digital Frequency Synthesizers using First-Order Polynomial Chebyshev Approximation 42
High Speed Galois Fields GF(2^m) Multipliers 41
Fixed-width Multipliers with Dual-tree Error Compensation 41
NORA based TDC in 90 nm CMOS 41
Totale 6.229
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Categoria #
all - tutte 27.123
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 27.123
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/202058 0 0 0 0 0 0 0 0 0 0 0 58
2020/2021445 9 39 26 45 42 51 44 18 45 28 33 65
2021/2022567 7 7 7 6 11 33 8 14 124 6 102 242
2022/2023833 115 92 38 76 106 109 5 86 124 13 50 19
2023/2024705 26 80 119 58 44 72 31 60 7 13 102 93
2024/20252.994 152 198 21 32 120 230 325 195 138 179 1.299 105
Totale 6.675