A wideband frequency synthesizer architecture is presented. The proposed topology employs a direct digital frequency synthesizer (DDFS) to control the output frequency of an offset-PLL. In this way, the synthesizer features a very fine frequency resolution, 24 Hz, as in delta-sigma fractional-N PLLs, but without being affected by the quantization-induced phase noise. This, in turn, allows enlarging the loop bandwidth. The frequency synthesizer is designed to be employed as a direct modulator for Bluetooth transmitter in a low-cost 0.35um CMOS technology. At 2.5 GHz it achieves 1.8-MHz bandwidth, while the settling time within 30 ppm for an 80-MHz step is 3 mu s. The integrated phase noise gives less than 1 degree of rms phase error and the worst-case spur is -48 dBc at 1 MHz, well below the specifications. Power dissipation is 120 mW for the PLL core, 50 mW for the DDFS plus DACs, and 19 mW for the GFSK modulator.
A 2.5GHz DDFS-PLL with 1.8MHz bandwidth in 0.35um CMOS / A., Bonfanti; DE CARO, Davide; A. D., Grasso; S., Pennisi; C., Samori; Strollo, ANTONIO GIUSEPPE MARIA. - In: IEEE JOURNAL OF SOLID-STATE CIRCUITS. - ISSN 0018-9200. - STAMPA. - 43:6(2008), pp. 1403-1413. [10.1109/JSSC.2008.922721]
A 2.5GHz DDFS-PLL with 1.8MHz bandwidth in 0.35um CMOS
DE CARO, Davide;STROLLO, ANTONIO GIUSEPPE MARIA
2008
Abstract
A wideband frequency synthesizer architecture is presented. The proposed topology employs a direct digital frequency synthesizer (DDFS) to control the output frequency of an offset-PLL. In this way, the synthesizer features a very fine frequency resolution, 24 Hz, as in delta-sigma fractional-N PLLs, but without being affected by the quantization-induced phase noise. This, in turn, allows enlarging the loop bandwidth. The frequency synthesizer is designed to be employed as a direct modulator for Bluetooth transmitter in a low-cost 0.35um CMOS technology. At 2.5 GHz it achieves 1.8-MHz bandwidth, while the settling time within 30 ppm for an 80-MHz step is 3 mu s. The integrated phase noise gives less than 1 degree of rms phase error and the worst-case spur is -48 dBc at 1 MHz, well below the specifications. Power dissipation is 120 mW for the PLL core, 50 mW for the DDFS plus DACs, and 19 mW for the GFSK modulator.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.