A new technique is presented for designing a parallel squarer that uses both the Booth-encoding and the 'traditional' folding technique. The proposed Booth-folding technique achieves a 50% reduction in the number of partial products with respect to the simple folding architecture, enabling the propagation delay and power dissipation to be significantly reduced.
Parallel squarer using Booth-folding technique / DE CARO, Davide; Strollo, ANTONIO GIUSEPPE MARIA. - In: ELECTRONICS LETTERS. - ISSN 0013-5194. - STAMPA. - 37:(2001), pp. 346-347. [10.1049/el:20010241]
Parallel squarer using Booth-folding technique
DE CARO, Davide;STROLLO, ANTONIO GIUSEPPE MARIA
2001
Abstract
A new technique is presented for designing a parallel squarer that uses both the Booth-encoding and the 'traditional' folding technique. The proposed Booth-folding technique achieves a 50% reduction in the number of partial products with respect to the simple folding architecture, enabling the propagation delay and power dissipation to be significantly reduced.File in questo prodotto:
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