Two novel low power flip-flops are presented in the paper. Proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. Presented circuits overcome the clock duty-cycle limitation of previously reported gated flipflops. Circuit simulations with the inclusion of parasitics show that sensible power dissipation reduction is possible if input signal has reduced switching activity. A 16-bit counter is presented as a simple low power application.
New clock gating techniques for low power flip-flops / Strollo, ANTONIO GIUSEPPE MARIA; Napoli, Ettore; DE CARO, Davide. - (2000), pp. 114-119. (Intervento presentato al convegno International Symposium on Low Power Electronics and Design (ISLPED 2000) tenutosi a Rapallo (Italy) nel Jul. 2000) [10.1109/LPE.2000.155263].
New clock gating techniques for low power flip-flops
STROLLO, ANTONIO GIUSEPPE MARIA;NAPOLI, ETTORE;DE CARO, Davide
2000
Abstract
Two novel low power flip-flops are presented in the paper. Proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. Presented circuits overcome the clock duty-cycle limitation of previously reported gated flipflops. Circuit simulations with the inclusion of parasitics show that sensible power dissipation reduction is possible if input signal has reduced switching activity. A 16-bit counter is presented as a simple low power application.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
