The paper describes the implementation of a 380 MHz, 13 bit, direct digital synthesizer/mixer IC in 0.25um CMOS technology. The circuit employs an innovative architecture which divides the pi/4 rotation operation required in the quadrature synthesizer/mixers, in three rotations. The first two rotations are implemented by using a CORDIC datapath completely realized in carry-save arithmetic. The directions of the CORDIC rotations are computed in parallel by using a little lookup table, for the first rotation, and a multiply by constant and addition circuit for the second rotation. The final (third) rotation is multiplier-based, in order to reduce the circuit latency and increase the circuit performances. The CORDIC datapath is implemented with a novel approach both at the algorithmic level and at the transistor level. At the algorithmic level the combined employ of sign-extension prevention, overflow prevention and a novel rounding scheme are presented. At the transistor level a design style that jointly uses full-CMOS and DPL to improve the circuit latency is described. The overall circuit performances are very interesting. The synthesizer/mixer IC, realized in a 0.25 um CMOS technology, has an area occupation of 0.22 mm2 and dissipates 152 mW at 380 MHz with a supply voltage of 2.5 V
A 380MHz Direct Digital Synthesizer/Mixer with Hybrid CORDIC Architecture in 0.25um CMOS / DE CARO, Davide; Petra, Nicola; Strollo, ANTONIO GIUSEPPE MARIA. - In: IEEE JOURNAL OF SOLID-STATE CIRCUITS. - ISSN 0018-9200. - STAMPA. - 42:1(2007), pp. 151-160. [10.1109/JSSC.2006.886527]
A 380MHz Direct Digital Synthesizer/Mixer with Hybrid CORDIC Architecture in 0.25um CMOS
DE CARO, Davide;PETRA, NICOLA;STROLLO, ANTONIO GIUSEPPE MARIA
2007
Abstract
The paper describes the implementation of a 380 MHz, 13 bit, direct digital synthesizer/mixer IC in 0.25um CMOS technology. The circuit employs an innovative architecture which divides the pi/4 rotation operation required in the quadrature synthesizer/mixers, in three rotations. The first two rotations are implemented by using a CORDIC datapath completely realized in carry-save arithmetic. The directions of the CORDIC rotations are computed in parallel by using a little lookup table, for the first rotation, and a multiply by constant and addition circuit for the second rotation. The final (third) rotation is multiplier-based, in order to reduce the circuit latency and increase the circuit performances. The CORDIC datapath is implemented with a novel approach both at the algorithmic level and at the transistor level. At the algorithmic level the combined employ of sign-extension prevention, overflow prevention and a novel rounding scheme are presented. At the transistor level a design style that jointly uses full-CMOS and DPL to improve the circuit latency is described. The overall circuit performances are very interesting. The synthesizer/mixer IC, realized in a 0.25 um CMOS technology, has an area occupation of 0.22 mm2 and dissipates 152 mW at 380 MHz with a supply voltage of 2.5 VFile | Dimensione | Formato | |
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DeCaro - JSSC 2007 - A 380MHz DDSM with Hybrid CORDIC.pdf
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