The hardware computation of the logarithm function is required in several applications, ranging from signal and image processing to telecommunication systems. In this brief we show that most of previous proposed logarithmic converters, based on piecewise linear approximations, suffer from large errors when dealing with fixed-point input values with many fractional bits, a situation often encountered in practical applications. Thus, we propose a novel logarithmic converter, using non uniform segmentation and piecewise linear approximation. A rigorous technique that allows computing the optimal segmentation and the coefficients values for a prescribed precision is described in the paper. For fixed-point input values, the proposed approach allows obtaining a sensibly lower error, for the same number of non-uniform segments, compared to previously published results. Implementation details and synthesis results in a 65nm CMOS technology are also presented.
Accurate Fixed-Point Logarithmic Converter / DE CARO, Davide; Genovese, Mariangela; Napoli, Ettore; Petra, Nicola; Strollo, ANTONIO GIUSEPPE MARIA. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS. - ISSN 1549-7747. - 61:7(2014), pp. 526-530. [10.1109/TCSII.2014.2327306]
Accurate Fixed-Point Logarithmic Converter
DE CARO, Davide;GENOVESE, MARIANGELA;NAPOLI, ETTORE;PETRA, NICOLA;STROLLO, ANTONIO GIUSEPPE MARIA
2014
Abstract
The hardware computation of the logarithm function is required in several applications, ranging from signal and image processing to telecommunication systems. In this brief we show that most of previous proposed logarithmic converters, based on piecewise linear approximations, suffer from large errors when dealing with fixed-point input values with many fractional bits, a situation often encountered in practical applications. Thus, we propose a novel logarithmic converter, using non uniform segmentation and piecewise linear approximation. A rigorous technique that allows computing the optimal segmentation and the coefficients values for a prescribed precision is described in the paper. For fixed-point input values, the proposed approach allows obtaining a sensibly lower error, for the same number of non-uniform segments, compared to previously published results. Implementation details and synthesis results in a 65nm CMOS technology are also presented.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.