Low-power approximate multiplier with error recovery using a new approximate 4-2 compressor

In this paper we propose an energy-efficient approximate multiplier which uses a new approximate 4-2 compressor. The proposed compressor has a low error probability and its error conditions can be easily detected. This, as previously shown in the literature, makes it possible to implement error recovery, when the compressor is used in the partial product reduction phase of a multiplier. Simulation results show that proposed approximate multipliers exhibit a sensible reduction in Mean Error Distance and in maximum Error Distance, compared to previous art. Application to an image processing task shows an improvement of about 8dB in peak signal-to-noise ratio. Implementation results in 28nm CMOS show that the electrical performance of multipliers designed with the novel circuit are close to the one obtained with previously proposed approximate compressors.