In this paper, a Reed-Solomon (RS) decoder for the widely used (255, 239) code is presented. The circuit exploits both a novel inversion-free Berlekamp-Massey algorithm architecture to solve the key-equation and a new bit-parallel Galois-field multiplier implementation to obtain increased circuit speed. Hardware sharing is widely used to reduce silicon area occupation. The proposed circuit, designed for a 0.25 μm CMOS technology, compares favourably with recently proposed RS decoders.

An area-efficient high-speed Reed-Solomon decoder in 0.25um CMOS

STROLLO, ANTONIO GIUSEPPE MARIA;DE CARO, Davide;NAPOLI, ETTORE;PETRA, NICOLA
2004

Abstract

In this paper, a Reed-Solomon (RS) decoder for the widely used (255, 239) code is presented. The circuit exploits both a novel inversion-free Berlekamp-Massey algorithm architecture to solve the key-equation and a new bit-parallel Galois-field multiplier implementation to obtain increased circuit speed. Hardware sharing is widely used to reduce silicon area occupation. The proposed circuit, designed for a 0.25 μm CMOS technology, compares favourably with recently proposed RS decoders.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11588/6667
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