In this paper, a Reed-Solomon (RS) decoder for the widely used (255, 239) code is presented. The circuit exploits both a novel inversion-free Berlekamp-Massey algorithm architecture to solve the key-equation and a new bit-parallel Galois-field multiplier implementation to obtain increased circuit speed. Hardware sharing is widely used to reduce silicon area occupation. The proposed circuit, designed for a 0.25 μm CMOS technology, compares favourably with recently proposed RS decoders.
An area-efficient high-speed Reed-Solomon decoder in 0.25um CMOS / Strollo, ANTONIO GIUSEPPE MARIA; DE CARO, Davide; Napoli, Ettore; Petra, Nicola. - (2004), pp. 479-482. (Intervento presentato al convegno Europen Solid-State circuit confefrence (ESSCIRC) tenutosi a Leuven, Belgio nel Sept. 2004) [10.1109/ESSCIR.2004.1356723].
An area-efficient high-speed Reed-Solomon decoder in 0.25um CMOS
STROLLO, ANTONIO GIUSEPPE MARIA;DE CARO, Davide;NAPOLI, ETTORE;PETRA, NICOLA
2004
Abstract
In this paper, a Reed-Solomon (RS) decoder for the widely used (255, 239) code is presented. The circuit exploits both a novel inversion-free Berlekamp-Massey algorithm architecture to solve the key-equation and a new bit-parallel Galois-field multiplier implementation to obtain increased circuit speed. Hardware sharing is widely used to reduce silicon area occupation. The proposed circuit, designed for a 0.25 μm CMOS technology, compares favourably with recently proposed RS decoders.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
