A new flip-flop is presented in which power dissipation is reduced by deactivating the clock signal on both the master and slave latches when there are no data transitions. The new circuit overcomes the clock duty-cycle constraints of previously proposed gated flip-flops. The power consumption of the presented circuit is significantly lower than that of a conventional flip-flop when the D input has a reduced switching activity.
Low power flip-flop with clock gating on master and slave latches / Strollo, ANTONIO GIUSEPPE MARIA; DE CARO, Davide. - In: ELECTRONICS LETTERS. - ISSN 0013-5194. - STAMPA. - 36:(2000), pp. 294-295. [10.1049/el:20000268]
Low power flip-flop with clock gating on master and slave latches
STROLLO, ANTONIO GIUSEPPE MARIA;DE CARO, Davide
2000
Abstract
A new flip-flop is presented in which power dissipation is reduced by deactivating the clock signal on both the master and slave latches when there are no data transitions. The new circuit overcomes the clock duty-cycle constraints of previously proposed gated flip-flops. The power consumption of the presented circuit is significantly lower than that of a conventional flip-flop when the D input has a reduced switching activity.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
