A new technique is presented for designing a parallel squarer that uses both the Boothencoding and the “traditional” Folding technique. The proposed Booth-Folding technique achieves a 50% reduction of the number of partial products with respect to the simple Folded architecture, allowing a remarkable reduction of propagation delay and power dissipation. In this paper a comparison between two 32-bit squarer circuits, one using the proposed Booth-Folding technique and one using the standard Folding technique, is presented. Simulation results show that a sensible improvement in area occupation, power dissipation and propagation delay is obtained using new squarer architecture.
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