Even if SiC MOSFETs technology has undergone huge progress in last years, there are some issues still open, such as high traps density at the SiO2/SiC interface. This work focuses on the measurement of the Gate capacitance when a DC bias is applied between Drain and Source to characterize the SiO2/SiC interface. The experimental curves, performed on a commercial SiC power MOSFET, exhibit a peak when the Gate voltage approaches the threshold voltage. Such peak is analyzed through TCAD simulations and its origin is addressed. Numerical analysis shows that this peak is associated to the displacement current, with a strong dependence on the traps concentration at the SiO2/SiC interface.
SiC MOSFET C-V Characteristics with Positive Biased Drain / Matacena, I.; Maresca, L.; Riccio, M.; Irace, A.; Breglio, G.; Daliento, S.; Castellazzi, A.. - 1062:(2022), pp. 653-657. (Intervento presentato al convegno 13th European Conference on Silicon Carbide and Related Materials, ECSCRM 2021 nel 2021) [10.4028/p-2tyqfr].
SiC MOSFET C-V Characteristics with Positive Biased Drain
Matacena I.;Maresca L.;Riccio M.;Irace A.;Breglio G.;Daliento S.;
2022
Abstract
Even if SiC MOSFETs technology has undergone huge progress in last years, there are some issues still open, such as high traps density at the SiO2/SiC interface. This work focuses on the measurement of the Gate capacitance when a DC bias is applied between Drain and Source to characterize the SiO2/SiC interface. The experimental curves, performed on a commercial SiC power MOSFET, exhibit a peak when the Gate voltage approaches the threshold voltage. Such peak is analyzed through TCAD simulations and its origin is addressed. Numerical analysis shows that this peak is associated to the displacement current, with a strong dependence on the traps concentration at the SiO2/SiC interface.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
