In this paper, two implementations of a SPICE-based compact model for SiC MOSFETs are presented. The two versions rely on widely adopted LEVEL-3 and BSIM 4.6.1 models, respectively. The paper discusses the feasibility of adopting these two models for the description of SiC power MOSFETs. Furthermore, after calibrating the DC characteristics on target experimental data coming from 1.7 kV-60 A MOSFETs, a comparison between the accuracy of the two is presented.
A Scalable SPICE Electrothermal Compact Model for SiC MOSFETs: A Comparative Study between the LEVEL-3 and the BSIM / Borghese, Alessandro.; Riccio, Michele.; Maresca, Luca; Breglio, Giovanni.; Irace, Andrea.. - 947:(2023), pp. 135-140. [10.4028/p-hmxz8o]
A Scalable SPICE Electrothermal Compact Model for SiC MOSFETs: A Comparative Study between the LEVEL-3 and the BSIM
Borghese Alessandro.
Primo
Writing – Original Draft Preparation
;Riccio Michele.;Maresca Luca;Breglio Giovanni.;Irace Andrea.
2023
Abstract
In this paper, two implementations of a SPICE-based compact model for SiC MOSFETs are presented. The two versions rely on widely adopted LEVEL-3 and BSIM 4.6.1 models, respectively. The paper discusses the feasibility of adopting these two models for the description of SiC power MOSFETs. Furthermore, after calibrating the DC characteristics on target experimental data coming from 1.7 kV-60 A MOSFETs, a comparison between the accuracy of the two is presented.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
