State-of-the-art Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are required to meet strict constraints on short-circuit capability, that are challenging to achieve due to the limited volume of the device compared to the silicon counterpart. This paper presents a novel device concept for a 1.2 kV SiC MOSFET that harnesses the potential of a composite silicon oxide/ferroelectric gate stack. Simple modeling suggests that the Curie-Weiss dependence of the dielectric constant of the ferroelectric layer can counterbalance the current increase due to the temperature during short-circuit. TCAD simulations demonstrate a substantial short-circuit ruggedness improvement since the maximum temperature in the device during short circuit events is lower with respect to a reference device with a standard oxide gate dielectric by a factor ½.

Substantial Improvement of the Short-circuit Capability of a 1.2 kV SiC MOSFET by a HfO2/SiO2Ferroelectric Gate Stack / Boccarossa, M.; Maresca, L.; Borghese, A.; Riccio, M.; Breglio, G.; Irace, A.; Salvatore, G. A.. - (2024), pp. 88-91. ( 36th International Symposium on Power Semiconductor Devices and ICs, ISPSD 2024 Bremen, Germany 2024) [10.1109/ISPSD59661.2024.10579678].

Substantial Improvement of the Short-circuit Capability of a 1.2 kV SiC MOSFET by a HfO2/SiO2Ferroelectric Gate Stack

Boccarossa M.
;
Maresca L.;Borghese A.;Riccio M.;Breglio G.;Irace A.;Salvatore G. A.
2024

Abstract

State-of-the-art Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are required to meet strict constraints on short-circuit capability, that are challenging to achieve due to the limited volume of the device compared to the silicon counterpart. This paper presents a novel device concept for a 1.2 kV SiC MOSFET that harnesses the potential of a composite silicon oxide/ferroelectric gate stack. Simple modeling suggests that the Curie-Weiss dependence of the dielectric constant of the ferroelectric layer can counterbalance the current increase due to the temperature during short-circuit. TCAD simulations demonstrate a substantial short-circuit ruggedness improvement since the maximum temperature in the device during short circuit events is lower with respect to a reference device with a standard oxide gate dielectric by a factor ½.
2024
9798350394825
Substantial Improvement of the Short-circuit Capability of a 1.2 kV SiC MOSFET by a HfO2/SiO2Ferroelectric Gate Stack / Boccarossa, M.; Maresca, L.; Borghese, A.; Riccio, M.; Breglio, G.; Irace, A.; Salvatore, G. A.. - (2024), pp. 88-91. ( 36th International Symposium on Power Semiconductor Devices and ICs, ISPSD 2024 Bremen, Germany 2024) [10.1109/ISPSD59661.2024.10579678].
File in questo prodotto:
Non ci sono file associati a questo prodotto.

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11588/1005138
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 2
  • ???jsp.display-item.citation.isi??? 2
social impact