Approximate computing is a new approach that can help to reduce power consumption in error-resilient applications. Although many works have been proposed for fixed-point multipliers with predetermined levels of accuracy, they are not able to adapt to a wide range of applications, that need floating-point calculations with time-varying requirements. In this paper, we introduce an adjustable floating-point multiplier in which groups of partial products can be dynamically truncated, while the approximation error is reduced with the help of a simple rounding technique. In the proposed floating-point multiplier, precision and power can be adjusted at run-time based on the users' requirements. The developed circuits are synthesized in TSMC 28 nm CMOS technology. The comparison with the state-of-the-art shows a good trade-off between error and power consumption. Furthermore, we demonstrate the suitability and versatility of our multiplier through image processing applications, proving that it can be usefully employed in real-world scenarios.

CFPM: Run-time Configurable Floating-Point Multiplier / Saggese, G.; Napoli, E.; Strollo, A. G. M.. - (2023), pp. 173-176. (Intervento presentato al convegno 18th International Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2023 tenutosi a City of Arts and Sciences and the Turia Gardens, esp nel 2023) [10.1109/PRIME58259.2023.10161866].

CFPM: Run-time Configurable Floating-Point Multiplier

Saggese G.;Napoli E.;Strollo A. G. M.
2023

Abstract

Approximate computing is a new approach that can help to reduce power consumption in error-resilient applications. Although many works have been proposed for fixed-point multipliers with predetermined levels of accuracy, they are not able to adapt to a wide range of applications, that need floating-point calculations with time-varying requirements. In this paper, we introduce an adjustable floating-point multiplier in which groups of partial products can be dynamically truncated, while the approximation error is reduced with the help of a simple rounding technique. In the proposed floating-point multiplier, precision and power can be adjusted at run-time based on the users' requirements. The developed circuits are synthesized in TSMC 28 nm CMOS technology. The comparison with the state-of-the-art shows a good trade-off between error and power consumption. Furthermore, we demonstrate the suitability and versatility of our multiplier through image processing applications, proving that it can be usefully employed in real-world scenarios.
2023
979-8-3503-0320-9
CFPM: Run-time Configurable Floating-Point Multiplier / Saggese, G.; Napoli, E.; Strollo, A. G. M.. - (2023), pp. 173-176. (Intervento presentato al convegno 18th International Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2023 tenutosi a City of Arts and Sciences and the Turia Gardens, esp nel 2023) [10.1109/PRIME58259.2023.10161866].
File in questo prodotto:
Non ci sono file associati a questo prodotto.

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11588/945727
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 0
  • ???jsp.display-item.citation.isi??? 0
social impact