Multispectral and Hyperspectral Images are widespread in Remote Sensing and Space Imaging Applications: they are typically three dimensional arrays of images and their raw content may include thousands of bands for a total of over a billion pixels. For adequate storing and transmission over satellite communication links a proper compression scheme is required. In this paper a FPGA implementation of the Consultative Committee for Space Data Systems (CCSDS) 123.0-B-1 standard algorithm is presented. The implementation results refer to a space-class device (Xilinx Virtex 5QV FX130T). The proposed architecture, composed by the Virtex5 FPGA and an external DRAM, implements circuital-oriented architectural improvements over the standard algorithm formulation. The proposed circuit, that is also user configurable in various aspects, overcomes the state of the art in terms of image pixel throughput (55.4 MSamples/s) and has a negligible footprint in terms of resource allocation (4%) for the selected FPGA.

FPGA implementation of the CCSDS-123.0-B-1 lossless Hyperspectral Image compression algorithm prediction stage

LOPEZ, GIORGIO;NAPOLI, ETTORE;STROLLO, ANTONIO GIUSEPPE MARIA
2015

Abstract

Multispectral and Hyperspectral Images are widespread in Remote Sensing and Space Imaging Applications: they are typically three dimensional arrays of images and their raw content may include thousands of bands for a total of over a billion pixels. For adequate storing and transmission over satellite communication links a proper compression scheme is required. In this paper a FPGA implementation of the Consultative Committee for Space Data Systems (CCSDS) 123.0-B-1 standard algorithm is presented. The implementation results refer to a space-class device (Xilinx Virtex 5QV FX130T). The proposed architecture, composed by the Virtex5 FPGA and an external DRAM, implements circuital-oriented architectural improvements over the standard algorithm formulation. The proposed circuit, that is also user configurable in various aspects, overcomes the state of the art in terms of image pixel throughput (55.4 MSamples/s) and has a negligible footprint in terms of resource allocation (4%) for the selected FPGA.
9781479983322
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11588/637718
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