Real time processing for SAR data is a very useful tool in civilian and military applications. However, in order to avoid resolution degradation, a very short time must be required for each single multiplication. This condition can be verified by using one-bit coded data and reference function: in fact, in this case operations can be performed by XNOR gates. In this paper, a VLSI architecture for real time one-bit processing is presented, and first performance tests are reported.
Novel VLSI architecture for real time operations of one-bit coded synthetic radar imaging data / C., Cimino; Franceschetti, Giorgio; Iodice, Antonio; Mazzeo, Antonino; Mazzocca, Nicola; Napoli, Ettore; Riccio, Daniele; P., Spirito; Strollo, ANTONIO GIUSEPPE MARIA; M., Tesauro. - 1:(1999), pp. 515-517. (Intervento presentato al convegno International Geoscience and Remote Sensing Symposium (IGARSS) tenutosi a Hamburg, Germany nel June 1999) [10.1109/IGARSS.1999.773551].
Novel VLSI architecture for real time operations of one-bit coded synthetic radar imaging data
FRANCESCHETTI, GIORGIO;IODICE, ANTONIO;MAZZEO, ANTONINO;MAZZOCCA, NICOLA;NAPOLI, ETTORE;RICCIO, DANIELE;STROLLO, ANTONIO GIUSEPPE MARIA;
1999
Abstract
Real time processing for SAR data is a very useful tool in civilian and military applications. However, in order to avoid resolution degradation, a very short time must be required for each single multiplication. This condition can be verified by using one-bit coded data and reference function: in fact, in this case operations can be performed by XNOR gates. In this paper, a VLSI architecture for real time one-bit processing is presented, and first performance tests are reported.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
