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EnglishA two-level carry-skip adder using complementary pass-transistor logic is presented in this paper. The proposed adder is fast, area efficient and highly modular. It is compared with a two-level carry-skip adder using CMOS logic, and with a carry-lookhaed adder automatically generated with the ALLIANCE CAD tools. SPICE simulations of the circuit extracted from the layout are used to evaluate the adder delay, while switch-level simulations are used to evaluate average power dissipation.
| Titolo: | A Fast and Area Efficient Complementary pass-transistor logic carry-skip adder | |
| Autori: | ||
| Data di pubblicazione: | 1997 | |
| Abstract: | A two-level carry-skip adder using complementary pass-transistor logic is presented in this paper. The proposed adder is fast, area efficient and highly modular. It is compared with a two-level carry-skip adder using CMOS logic, and with a carry-lookhaed adder automatically generated with the ALLIANCE CAD tools. SPICE simulations of the circuit extracted from the layout are used to evaluate the adder delay, while switch-level simulations are used to evaluate average power dissipation. | |
| Handle: | http://hdl.handle.net/11588/189797 | |
| ISBN: | 9780780336643 0-7803-3664-X | |
| Appare nelle tipologie: | 4.1 Articoli in Atti di convegno |
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