A novel architecture for real time Synthetic Aperture Radar (SAR) signal processing is presented. Presently, notwithstanding the use of expensive parallel computers and FET techniques, available SAR processors are unable to achieve real time performance. The proposed architecture achieves real time processing by using a recently proposed signum coded algorithm and time domain processing implemented in a custom VLSI architecture based on systolic arrays
A VLSI processor for light-weight real-time SAR imaging using signum coded signal and time domain processing / Strollo, ANTONIO GIUSEPPE MARIA; Napoli, Ettore; C., Cimino. - STAMPA. - 3:(1999), pp. 1631-1634. (Intervento presentato al convegno ICECS'99 tenutosi a Pafos, Cyprus nel 5-8 August, 1999) [10.1109/ICECS.1999.814486].
A VLSI processor for light-weight real-time SAR imaging using signum coded signal and time domain processing
STROLLO, ANTONIO GIUSEPPE MARIA;NAPOLI, ETTORE;
1999
Abstract
A novel architecture for real time Synthetic Aperture Radar (SAR) signal processing is presented. Presently, notwithstanding the use of expensive parallel computers and FET techniques, available SAR processors are unable to achieve real time performance. The proposed architecture achieves real time processing by using a recently proposed signum coded algorithm and time domain processing implemented in a custom VLSI architecture based on systolic arraysI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
