A comprehensive analysis of double edge-triggered (DET) flip-flops’ power dissipation, taking into account input signal statistics, is presented in this paper. It is shown that using DET instead of a single edge-triggered flip-flop may result in significant energy savings if the input signal has reduced activity. On the other hand, the high switching rate of DET internal nodes may result in larger power dissipation if the input signal has a high transition probability or significant glitching.
Analysis of Power Dissipation in Double Edge Triggered Flip-Flops / Strollo, ANTONIO GIUSEPPE MARIA; Napoli, Ettore; C., Cimino. - In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. - ISSN 1063-8210. - STAMPA. - 8:5(2000), pp. 624-628. [10.1109/92.894168]
Analysis of Power Dissipation in Double Edge Triggered Flip-Flops
STROLLO, ANTONIO GIUSEPPE MARIA;NAPOLI, ETTORE;
2000
Abstract
A comprehensive analysis of double edge-triggered (DET) flip-flops’ power dissipation, taking into account input signal statistics, is presented in this paper. It is shown that using DET instead of a single edge-triggered flip-flop may result in significant energy savings if the input signal has reduced activity. On the other hand, the high switching rate of DET internal nodes may result in larger power dissipation if the input signal has a high transition probability or significant glitching.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
