A low power double edge-triggered (DET) flip-flop using a single latch is presented. In the proposed circuit data is sampled into the latch during a short transparency period for each edge of the clock signal. The proposed flip-flop requires small silicon area and has lower power dissipation with respect to previously reported DET flip-flops.
Low power double edge-triggered flip-flop using one latch / Strollo, ANTONIO GIUSEPPE MARIA; Napoli, Ettore; C., Cimino. - In: ELECTRONICS LETTERS. - ISSN 0013-5194. - STAMPA. - 35:4(1999), pp. 187-188. [10.1049/el:19990164]
Low power double edge-triggered flip-flop using one latch
STROLLO, ANTONIO GIUSEPPE MARIA;NAPOLI, ETTORE;
1999
Abstract
A low power double edge-triggered (DET) flip-flop using a single latch is presented. In the proposed circuit data is sampled into the latch during a short transparency period for each edge of the clock signal. The proposed flip-flop requires small silicon area and has lower power dissipation with respect to previously reported DET flip-flops.File in questo prodotto:
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