Advances in Adapting Memory-Bound CFD Computations to RISC-V Multicore Architecture

This paper tackles the challenge of adapting HPC codes to RISC-V architecture for real-world applications with memory-bound numerical codes. The Multidimensional Positive Definite Advection Transport Algorithm (MPDATA) application is the code we study as a use case. This work explores whether the methodology developed in our previous works for Intel and AMD x86 architectures can address performance trade-offs and bottlenecks of multicore RISC-V computing platforms while executing the memory-bound MPDATA code. The explored platforms include: (i) Banana Pi BPI-F3 low-power platform, and (ii) Milk-V system with the 64-core Sophon SG2042 processor. Special emphasis is given to efficient vectorization and using lower-precision computations. Besides performance, energy consumption is studied as well.