Virtual Scan Chains for online testing of FPGA-based embedded systems

This paper presents a technique for online testing of digital designs implemented on an FPGA. The approach enables application-oriented testing, in that it covers the subset of the FPGA which is actually used for the implemented design, and considers scenarios where the FPGA component is a part of a larger embedded system. The proposed approach is in fact based on a software framework, which acts as an abstraction layer for reconfigurable hardware resources. Essentially, the framework exposes to software applications a Register-Transfer Level view of the underlying hardware, allowing test procedures to be implemented as software programs. Our approach is especially advantageous when memory is a constraint, the case of many embedded systems. As proved by experimental results, in fact, test procedures turn out to be very compact and much more memory-efficient than conventional approaches relying on static sets of FPGA testing configurations to be stored in the system memory.