In the recent years, Approximate Computing (AxC) has emerged as a new paradigm for energy efficient design of Integrated Circuits (ICs). AxC is based on the intuitive observation that, while performing exact computation requires a high amount of resources, allowing a selective approximation or an occasional relaxation of the specifications can provide significant gains in area, performances and energy efficiency. This work focuses on a case study about functional approximation of digital circuits. The functional approximation aims at modifying the circuit structure so that the original function F will be replaced by G whose implementation leads to area/energy reduction at the cost of reduced accuracy (i.e., some errors can be observed at the outputs of G). In this paper, we investigate an approach for the functional approximation exploiting fault simulation. Preliminary results show the potentiality of this approach in terms of area reduction.

Towards digital circuit approximation by exploiting fault simulation / Traiola, M.; Virazel, A.; Girard, P.; Barbareschi, M.; Bosio, A.. - (2017), pp. 1-7. (Intervento presentato al convegno 2017 IEEE East-West Design and Test Symposium, EWDTS 2017 tenutosi a srb nel 2017) [10.1109/EWDTS.2017.8110108].

Towards digital circuit approximation by exploiting fault simulation

Barbareschi M.;
2017

Abstract

In the recent years, Approximate Computing (AxC) has emerged as a new paradigm for energy efficient design of Integrated Circuits (ICs). AxC is based on the intuitive observation that, while performing exact computation requires a high amount of resources, allowing a selective approximation or an occasional relaxation of the specifications can provide significant gains in area, performances and energy efficiency. This work focuses on a case study about functional approximation of digital circuits. The functional approximation aims at modifying the circuit structure so that the original function F will be replaced by G whose implementation leads to area/energy reduction at the cost of reduced accuracy (i.e., some errors can be observed at the outputs of G). In this paper, we investigate an approach for the functional approximation exploiting fault simulation. Preliminary results show the potentiality of this approach in terms of area reduction.
2017
978-1-5386-3299-4
Towards digital circuit approximation by exploiting fault simulation / Traiola, M.; Virazel, A.; Girard, P.; Barbareschi, M.; Bosio, A.. - (2017), pp. 1-7. (Intervento presentato al convegno 2017 IEEE East-West Design and Test Symposium, EWDTS 2017 tenutosi a srb nel 2017) [10.1109/EWDTS.2017.8110108].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11588/915815
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