Protocol-independent, fixed-latency links with FPGA-embedded SerDeses

Most high-speed Serializer-Deserializer (SerDes) chips have a random latency through the data-path each time the link is established (e.g. after a reset, a loss of signal or a power cycle). However, there are fields of applications, such as timing synchronization, radio equipment control and trigger systems of High Energy Physics experiments that would benefit from fixed-latency links. In this paper, we present a link architecture based on high-speed SerDeses circuits embedded in Field Programmable Gate Array (FPGAs). Our architecture works with fixed-latency, it is independent of the protocol and can be customized to support any. As an example of implementation, we report on a synchronous 2.5-Gbps 8B10B serial link. © 2012 IOP Publishing Ltd and Sissa Medialab srl.