A JESD204B-Compliant Architecture for Remote and Deterministic-Latency Operation

High-speed analog-to-digital converters (ADCs) are key components in a huge variety of systems, including trigger and data acquisition (TDAQ) systems of nuclear and subnuclear physics experiments. Over the last decades, the sample rate and dynamic range of high-speed ADCs underwent a continuous growth, and it required the development of suitable interface protocols, such as the new JESD204B serial interface protocol. In this paper, we present an original JESD204B-compliant architecture we designed, which is able to operate an ADC in a remote fashion. Our design includes a deterministic-latency high-speed serial link, which is the only connection between the local and remote logic of the architecture and which preserves the deterministic timing features of the protocol. By means of our solution, it is possible to read data out of several converters, even remote to each other, and keep them operating synchro-nously. Our link also supports forward error correction (FEC) capabilities, in the view of the operation in radiation areas (e.g., on-detector in TDAQ systems). We describe an implementation of our concept in a latest generation field programmable gate array (Xilinx Kintex-7 325T) for reading data from a high-speed JESD204B-compliant ADC. We present measurements of the jitter of JESD204B timing-critical signals forwarded over the link and of latency determinism of the FEC-protected link.