Implementation of high-resolution time-to-digital converters on two different FPGA devices

This paper describes the development of two high precision Time-to-Digital Converter (TDC) in two different SRAM-based FPGA devices. The time conversion is based on a course counter for long range and on a stabilised delay line for the time interpolation within the system clock cycle. In the first method, dedicated carry lines are used to perform fine time measurement, while in the second one a differential tapped delay line is used. In this paper we compare the two architectures and show their performance in terms of stability and resolution.