Multi-Physics Simulations of a 1.2 kV Embedded SiC Prepackage

Embedding represents a game-changing packaging strategy for wide-bandgap semiconductors, slashing parasitic impedances to enable faster, cleaner switching, lower losses, and higher frequencies. Yet questions about reliability, scalability, and heat management persist. Here, we use multiphysics finite-element simulations to explore an embedded half-bridge of two 1.2 kV SiC MOSFETs across a range of commercial insulated substrates - alumina, Si3N4, AlN, and IMS with varying layer thicknesses. A Pareto-based thermomechanical optimization pinpoints aluminum nitride as the best configuration, delivering 0.27K/W thermal resistance, 0.2 % plastic strain, and 1.9 % creep strain during sintering. Creep concentrates in the silver sinter layer, matching experimental observations, underscoring the need to address time-dependent deformation in reliability assessments. A major improvement is achieved by redesigning the top copper interconnect from a solid block to a pillar like geometry, which reduces creep strain in the sintered layer by four times. We also identify a critical sintering cool-down rate above which creep vanishes and only plastic strain remains providing a new lever for process control. Finally, we demonstrate scalability by paralleling four optimized prepackages into a power module with just 3 nH of stray inductance, ready for high-frequency, high-efficiency conversion.