A two-level carry-skip adder using complementary pass-transistor logic is presented in this paper. The proposed adder is fast, area efficient and highly modular. It is compared with a two-level carry-skip adder using CMOS logic, and with a carry-lookhaed adder automatically generated with the ALLIANCE CAD tools. SPICE simulations of the circuit extracted from the layout are used to evaluate the adder delay, while switch-level simulations are used to evaluate average power dissipation.
A Fast and Area Efficient Complementary pass-transistor logic carry-skip adder / Strollo, ANTONIO GIUSEPPE MARIA; Napoli, Ettore. - STAMPA. - (1997), pp. 701-704. (Intervento presentato al convegno International Conference on Microelectronics (MIEL'97). tenutosi a Nis, Serbia nel 14-17 September 1997) [10.1109/ICMEL.1997.632941].
A Fast and Area Efficient Complementary pass-transistor logic carry-skip adder
STROLLO, ANTONIO GIUSEPPE MARIA;NAPOLI, ETTORE
1997
Abstract
A two-level carry-skip adder using complementary pass-transistor logic is presented in this paper. The proposed adder is fast, area efficient and highly modular. It is compared with a two-level carry-skip adder using CMOS logic, and with a carry-lookhaed adder automatically generated with the ALLIANCE CAD tools. SPICE simulations of the circuit extracted from the layout are used to evaluate the adder delay, while switch-level simulations are used to evaluate average power dissipation.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.